V-by-One HS is developed by THine to support higher frame rates and resolutions of advance flat panel display technology. The unique variable speed technology, which data rate from 600Mbps to 4Gbps, effectively meets the requirements of different pixel rates. The equalizer technology from THine achieves high video signal quality at the same time reducing total cost by enabling the use of low cost connectors, cables and reducing components for EMI control.
V-by-One HS using Clock and Data Recovery (CDR) technology solves skew problems and eliminates the need of fixed frequency signal such as clock, which results in low EMI noises. V-by-One HS also helps to reduce the number of cable by exist THine SerDes technology, it achieves 4Gbps transmission per pair of cable.
THCV217 and THCV218 are designed to support high speed video signal transmission between host and display. The two high speed data lanes with maximum serial data rate 3.4Gbps/lane support video up to 1080p/60Hz/30bits or 4k2k/30Hz/16bits colors. It suitable for applications like TV, surveillance camera, multifunction printer, projector and medical equipment.
Color depth selectable: 24(8×3)/32(10×3)bit
Single-in/Single-out, Single-in/Dual-out and Dual-in/Dual-out selectable for THCV217
Single-in/Single-out, Dual-in/Single-out and Dual-in/Dual-out selectable for THCV218
AC coupling for high speed lines
CORE 1.8V, CMOS IO 3.3V
Wide frequency range from 20MHz to 85MHz, or 40MHz to 170MHz
Spread Spectrum Clocking tolerant up to 30kHz±5% (center spread)
Operating temperature: -20 to 85°C
THCV217 is using TFBGA105 packaging, THCV218 is using TFBGA145 packaging
Need more information about our V by One HS solution? Drop us an email and we will come back to you.
THC63LVD104C is Thine LVDS receiver capable of supporting data transmission between host and TFT display, up to SXGA resolution. This IC chip converts LVDS data streams into CMOS/TTL signal, either by the rising edge or falling edge of the clock signal.
Features of THC63LVD104C
Wide dot clock range from 8MHz to 12MHz suitable for NTSC and up to SXGA resolution
PLL allow no external components
output clock duty cycle is 50%
TTL clock is edge programmable
Power down mode is available
Single 3.3V CMOS low power design
come with 64pin TQFP
fail-safe mode for open LVDS input
Application of THC63LVD104C
Thine LVDS receiver THC63LVD104C can be used in IP Security Camera. It allows high resolution image to be captured and transmit the data through LVDS signalling.
Looking for our Thine LVDS transmitter or receiver ICs for your production needs? Feel free to contact us and we will response to your enquiry in soonest time.
THC63LVD1023B is Thine LVDS transmitter designing to support transmission link between host and display. It converts CMOS/TTL data bits into LVDS data stream. There is a dedicated pin on the chip to be programmed for rising edge or falling edge clocks.
flexible input/output mode
single/dual TTL in, single/dual LVDS out
double edge input for single TTL in/dual LVDS out
input port SW for single TTL in/dual LVDS out
asynchronous dual TTL in/dual LVDS out
clock edge selectable
PLL requires. No external components
3 LVDS data mapping for simplifying PCB layout
pseudo random pattern generation circuit
support reduced swing LVDS for low EMI
power down mode
low power single 3.3V CMOS design
backward compatible with THC63LVD1023
wide dot clock range suited for TV signal (480i-1080p), PC signal (VGA-XGA)